The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device capable of reducing additional circuits required in a test operation after a large-capacity semiconductor memory device is fabricated.
In a system with a variety of semiconductor devices, a semiconductor memory device serves as a data storage. The semiconductor memory device outputs data corresponding to addresses received from a data processor, e.g., a central processing unit (CPU), or stores data received from the data processor into memory cells selected by addresses.
As the operating speed of the system increases and semiconductor integrated circuit technologies are advanced, semiconductor memory devices are required to input and output data at higher speed. In recent years, there is a demand for a semiconductor memory device capable of storing a larger amount of data and reading/writing data at faster speed. Hence, design and fabrication of the semiconductor memory device become more complex, and a test operation of the semiconductor memory device also becomes complex. The number of operations to be tested increases, and the test operations becomes complex, leading to the increase of a test time. Therefore, the mass production of the semiconductor memory device becomes increasingly more difficult. Many efforts have been made to prevent the reduction of productivity.
FIG. 1 is a block diagram of a conventional semiconductor memory device.
Referring to FIG. 1, the conventional semiconductor memory device includes a plurality of bands 120_0 to 120_3, a bank controller 140 for enabling the banks 120_0 to 120_3, and a plurality of data pads 160_1 through 160_4 through which data output from the banks 120_0 to 120_3 are output to the outside. Although FIG. 1 illustrates the data pads used to transfer data output from the banks in a test operation after the fabrication of the semiconductor memory device, more data pads are included in the semiconductor memory device.
When a read or write command is input to a semiconductor memory device in a test operation, the bank controller 10 simultaneously activates bank select signals STROBE_0 to STROBE_3 for selecting the respective banks 120_0 to 120_3. When the write command is input, data input through the data pads 160_1 to 160_4 are stored in the selected banks 120_0 to 120_3. When the read command is input, data stored in the selected banks 120_0 to 120_3 are output through the data pads 160_1 to 160_4.
FIG. 2 is a timing diagram illustrating data input/output timing of the conventional semiconductor memory device of FIG. 1. It is assumed that a write latency (WL) is 1tCK, a column address strobe (CAS) latency (CL) is 2tCK, and a burst length (BL) is 4.
Referring to FIG. 2, when a write command WT is input to the semiconductor memory device, write data are input through the data pads 160_0 to 160_4 after a write latency (WL). The input write data are transferred through global input/output lines GIO_0<0:3> to GIO_3<0:3> to banks 120_0 to 120_3 selected by bank select signals STROBE_0 to STROBE_3 activated in response to the write command WT.
When a read command RD is input, stored data are output through the data pads 160_1 to 160_4 after a CAS latency (CL). The bank controller 140 enables the bank select signals STROBE_0 to STROBE_3 in response to the read command RD, and data output from the banks 120_0 to 120_3 selected in response to the bank select signals STROBE_0 to STROBE_3 are transferred to the data pads 160_1 to 160_4. At this point, the input or output data are transferred in synchronization with rising and falling edges of a system clock CLK. In addition, four data per data pad are successively transferred according to the burst length (BL).
The conventional semiconductor memory device uses four data pads 160_1 to 160_4 to test the data input and output operations. Therefore, in order to test data input or output through the four data pads 160_1 to 160_4, four channels of a test apparatus must be allocated. That is, at least four channels are allocated in the semiconductor memory device in order to test a basic operation of the semiconductor memory device, such as the data input and output operations.
As the operating speed of the semiconductor memory device is gradually increasing and the semiconductor memory device is highly integrated, the internal structure and operation becomes more complex and the test operation also becomes more complex. A test time can be reduced by allocating more channels of the test apparatus to the semiconductor memory device. However, in this case, a manufacturing cost increases because more test apparatuses are used. Therefore, there is a demand for a method and internal structure capable of improving the productivity by minimizing the test time. Especially, four data pads are used to test the data input and output operations, and four channels of the test apparatus are allocated. Thus, the number of semiconductor memory devices the test apparatus can simultaneously test is reduced and it takes a lot of time to test a large number of semiconductor memory devices.